Paging Simulator

Architecture Level: Binary Translation

CPU (Logical Address)
Page (p) 0 00
Offset (d) 0 00
4 Bits Total
Page Table
Page (p)Frame (f)
Physical Address Reg
Frame (f) - ---
Offset (d) - --
5 Bits Total (3+2)
Physical Memory (RAM)
Frame No.Content
Logical Memory
Physical Memory
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